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? motorola, inc. 2004 motorola semiconductor technical data order number: MPC962305 rev 5, 08/2004 low-cost 3.3 v zero delay buffer the mpc962309 is a zero delay buffer designed to distribute high-speed clocks. available in a 16-pin soic or tssop package, the device accepts one reference input and drives nine low-skew clocks. the MPC962305 is the 8-pin version of the mpc962309 which drives five outputs with one reference input. the -1h versions of these devices have higher drive than the -1 devices and can operate up to 100/-133 mhz freq uencies. these parts have on-chip plls which lock to an input clock presented on the ref pin. the pll feedback is on-chip and is obtained from the clockout pad. features ? 1:5 lvcmos zero-delay buffer (MPC962305) ? 1:9 lvcmos zero-delay buffer (mpc962309) ? zero input-output propagation delay ? multiple low-skew outputs ? 250 ps max output-output skew ? 700 ps max device-device skew ? supports a clock i/o frequency range of 10 mhz to 133 mhz, compatible with cpu and pci bus frequencies ? low jitter, 200 ps max cycle-cycl e, and compatible with pentium ? based systems ? test mode to bypass pll (mpc962309 only. see ?select input decoding?) ? 8-pin soic or 8-pin t ssop package (MPC962305);16-pin soic or 16-pin tssop package (mpc962309) ? single 3.3 v supply ? ambient temperature range: ?40 c to +85 c ? compatible with the cy2305, cy23s05, cy2309, cy23s09 ? spread spectrum compatible functional description the mpc962309 has two banks of four outputs each, which can be con- trolled by the select inputs as shown in table 3.select input decoding for mpc962309 . bank b can be tri-stated if all of the outputs are not require d. select inputs also allow the input clock to be directly appl ied to the outputs for chip and system testing purposes. the MPC962305 and mpc962309 plls enters a power down state w hen there are no rising edges on the ref input. during this state, all of the outputs are in tristate, the pll is turned off, and there is less than 25.0 a of current draw for the device. the pll shuts down in one additional case as shown in table 3.select input decoding for mpc962309 . multiple MPC962305 and mpc962309 devices can accept the same input clock and distribute it throughout the system. in this situation, the difference between the output skews of two devices will be less than 700 ps. all outputs have less than 200 ps of cycle-cycle jitt er. the input-to-output propagation delay on both devices is guaranteed to be less than 350 ps and the output-to-output ske w is guaranteed to be less than 250 ps. the MPC962305 and mpc962309 are available in two/three different configurations, as shown on the ordering information page. the MPC962305-1/mpc962309-1 are the base parts. high drive versions of those devices, MPC962305-1h and mpc962309-1h, are available to provide faster rise and fall times of the base device. MPC962305 mpc962309 d suffix 16-lead soic package case 751b-05 dt suffix 16-lead tssop package case 948f-01 d suffix 8-lead soic package case 751-06 dt suffix 8-lead tssop package case 948j-01 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC962305 mpc962309 timing solutions 2 motorola table 1. pin description for mpc962309 pin signal description 1 ref 1 input reference frequency, 5 v-tolerant input 2 clka1 2 buffered clock output, bank a 3 clka2 2 buffered clock output, bank a 4v dd 3.3 v supply 5 gnd ground 6 clkb1 2 buffered clock output, bank b 7 clkb2 2 buffered clock output, bank b 8 s2 3 select input, bit 2 9 s1 3 select input, bit 1 10 clkb3 2 buffered clock output, bank b 11 clkb4 2 buffered clock output, bank b 12 gnd ground 13 v dd 3.3 v supply 14 clka3 2 buffered clock output, bank a 15 clka4 2 buffered clock output, bank a 16 clkout 2 buffered output, internal feedback on this pin 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 clkout clka4 clka3 v dd gnd clkb4 clkb3 s1 ref clka1 clka2 v dd gnd clkb1 clkb2 s2 soic/tssop top view pin configuration clka1 clka2 clka3 clka4 clkb1 clkb2 clkb3 clkb4 clkout pll mux select input decoding s2 s1 ref block diagram 1 2 3 4 8 7 6 5 clkout clk4 v dd clk3 ref clk2 clk1 gnd soic/tssop top view table 2. pin description for MPC962305 pin signal description 1 ref 1 input reference frequency, 5 v-tolerant input 2 clk2 2 buffered clock output 3 clk1 2 buffered clock output 4 gnd ground 5 clk3 2 buffered clock output 6 v dd 3.3 v supply 7 clk4 2 buffered clock output 8 clkout 2 buffered clock output, internal feedback on this pin 3 1. weak pull-down. 2. weak pull-down on all outputs. 3. weak pull-ups on these inputs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC962305 mpc962309 motorola 3 timing solutions table 3. select input decoding for mpc962309 s2 s1 clock a1?a4 clock b1?b4 clkout 1 1. this output is driven and has an internal feedback for the pll. the load on this output can be adjusted to change the skew b etween the reference and output. output source pll shutdown 0 0 three-state three-state driven pll n 0 1 driven three-state driven pll n 1 0 driven driven driven reference y 1 1 driven driven driven pll n table 4. maximum ratings characteristics value unit supply voltage to ground potential ? 0.5 to +3.9 v dc input voltage (except ref) ? 0.5 to v dd +0.5 v dc input voltage ref ? 0.5 to 5.5 v storage temperature ? 65 to +150 c junction temperature 150 c static discharge voltage (per mil-std-883, method 3015) >2000 v table 5. operating conditions for MPC962305-x and mpc962309-x industrial temperature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) ? 40 85 c c l load capacitance, below 100 mhz 30 pf c l load capacitance, from 100 mhz to 133 mhz 10 pf c in input capacitance 7 pf table 6. electrical ch aracteristics for MPC962305-x and mpc962 309-x industrial temperature devices 1 parameter description test conditions min max unit v il input low voltage 2 0.8 v v ih input high voltage 2 2.0 v i il input low current v in = 0 v 50.0 a i ih input high current v in = v dd 100.0 a v ol output low voltage 3 i ol = 8 ma ( ? 1) i oh = 12 ma ( ? 1h) 0.4 v v oh output high voltage 3 i oh = ? 8 ma ( ? 1) i ol = ? 12 ma ( ? 1h) 2.4 v i dd (pd mode) power down supply current ref = 0 mhz 25.0 a i dd supply current unloaded outputs at 66.67 mhz, sel inputs at v dd 35.0 ma 1. all parameters are s pecified with loaded outputs. 2. ref input has a threshold voltage of v pp /2. 3. parameter is guaranteed by design and characterization. not 100% tested in production. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC962305 mpc962309 timing solutions 4 motorola table 7. switching characterist ics for MPC962305-1 and mpc962309-1 industrial temperature devices 1 1. all parameters are s pecified with loaded outputs. parameter name test conditions min typ max unit t 1 output frequency 30-pf load 10-pf load 10 10 100 133.33 mhz mhz duty cycle 2 = t 2 t 1 2. parameter is guaranteed by design and characterization. not 100% tested in production. measured at 1.4 v, f out = 66.67 mhz 40.0 50.0 60.0 % t 3 rise time 2 measured between 0.8 v and 2.0 v 2.50 ns t 4 fall time 2 measured between 0.8 v and 2.0 v 2.50 ns t 5 output to output skew 2 all outputs equally loaded 250 ps t 6a delay, ref rising edge to clkout rising edge 2 measured at v dd /2 0 350 ps t 6b delay, ref rising edge to clkout rising edge 2 measured at v dd /2. measured in pll bypass mode, mpc962309 device only 158.7ns t 7 device to device skew 2 measured at v dd /2 on the clkout pins of devices 0700ps t j cycle to cycle jitter 2 measured at 66.67 mhz, loaded outputs 200 ps t lock pll lock time 2 stable power supply, valid clock presented on ref pin 1.0 ms table 8. switching characterist ics for MPC962305-1h and mpc962309- 1h industrial temperature devices 1 1. all parameters are s pecified with loaded outputs. parameter name test conditions min typ max unit t 1 output frequency 30-pf load 10-pf load 10 10 100 133.33 mhz mhz duty cycle 2 = t2 t1 2. parameter is guaranteed by design and characterization. not 100% tested in production. measured at 1.4 v, f out = 66.67 mhz 40.0 50.0 60.0 % duty cycle 2 = t2 t1 measured at 1.4 v, f out < 50 mhz 45.0 55.0 55.0 % t 3 rise time 2 measured between 0.8 v and 2.0 v 1.50 ns t 4 fall time 2 measured between 0.8 v and 2.0 v 1.50 ns t 5 output to output skew 2 all outputs equally loaded 250 ps t 6a delay, ref rising edge to clkout rising edge 2 measured at v dd /2 0 350 ps t 6b delay, ref rising edge to clkout rising edge 2 measured at v dd /2. measured in pll bypass mode, mpc962309 device only 158.7ns t 7 device to device skew 2 measured at v dd /2 on the clkout pins of devices 0700ps t 8 output slew rate 2 measured between 0.8 v and 2.0 v using test circuit #2 1v/ns t j cycle to cycle jitter 2 measured at 66.67 mhz, loaded outputs 200 ps t lock pll lock time 2 stable power supply, valid clock presented on ref pin 1.0 ms f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC962305 mpc962309 motorola 5 timing solutions applications information figure 1. outpu t-to-output skew t sk(o) figure 2. static phase offset test reference figure 3. output duty cycle (dc) v cc v cc 2 gnd v cc v cc 2 gnd t 6 cclk fb_in the pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device v cc 1.4 v gnd v cc 1.4 v gnd t 5 the time from the pll controlled edge to the non-controlled edge, divided by the time between pll controlled edges, expressed as a percentage v cc 1.4 v gnd t 2 t 1 dc = t 2 /t 1 x 100% figure 5. cycle-to-cycle jitter t 4 t 3 v cc = 3.3 v 2.0 0.8 figure 6. output transition time test reference the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs t n t j = | t n ?t n+1 | t n+1 figure 4. device-to-device skew v cc v cc 2 gnd v cc v cc 2 gnd t 7 device 1 device 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC962305 mpc962309 timing solutions 6 motorola table 9. ordering information ordering code package type MPC962305d-1 8-pin 150-mil soic MPC962305d-1r2 8-pin 150-mil soic-tape and reel MPC962305d-1h 8-pin 150-mil soic MPC962305d-1hr2 8-pin 150-mil soic-tape and reel MPC962305dt-1h 8-pin 150-mil tssop MPC962305dt-1hr2 8-pin 150-mil tssop-tape and reel mpc962309d-1 16-pin 150-mil soic mpc962309d-1r2 16-pin 150-mil soic-tape and reel mpc962309d-1h 16-pin 150-mil soic mpc962309d-1hr2 16-pin 150-mil soic-tape and reel mpc962309dt-1h 16-pin 4.4-mm tssop mpc962309dt-1hr2 16-pin 4.4-mm tssop-tape and reel 0.1 f 0.1 f clk out c load v dd v dd outputs gnd gnd test circuit #1 test circuit for all parameters except t 8 0.1 f 0.1 f clk out 10 pf v dd v dd outputs gnd gnd test circuit #2 test circuit for t 8 , output slew rate on ?1h, ?5 device 1 k ? 1 k ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC962305 mpc962309 motorola 7 timing solutions package dimensions style 4: pin 1. anode 2. anode 3. anode 4. anode 5. anode 6. anode 7. anode 8. common cathode style 1: pin 1. emitter 2. collector 3. collector 4. emitter 5. emitter 6. base 7. base 8. emitter style 2: pin 1. collector, die, #1 2. collector, #1 3. collector, #2 4. collector, #2 5. base, #2 6. emitter, #2 7. base, #1 8. emitter, #1 style 3: pin 1. drain, die #1 2. drain, #1 3. drain, #2 4. drain, #2 5. gate, #2 6. source, #2 7. gate, #1 8. source, #1 style 6: pin 1. source 2. drain 3. drain 4. source 5. source 6. gate 7. gate 8. source style 5: pin 1. drain 2. drain 3. drain 4. drain 5. gate 6. gate 7. source 8. source style 7: pin 1. input 2. external bypass 3. third stage source 4. ground 5. drain 6. gate 3 7. second stage vd 8. first stage vd style 8: pin 1. collector, die #1 2. base, #1 3. base, #2 4. collector, #2 5. collector, #2 6. emitter, #2 7. emitter, #1 8. collector, #1 style 9: pin 1. emitter, common 2. collector, die #1 3. collector, die #2 4. emitter, common 5. emitter, common 6. base, die #2 7. base, die #1 8. emitter, common style 10: pin 1. ground 2. bias 1 3. output 4. ground 5. ground 6. bias 2 7. input 8. ground style 11: pin 1. source 1 2. gate 1 3. source 2 4. gate 2 5. drain 2 6. drain 2 7. drain 1 8. drain 1 style 12: pin 1. source 2. source 3. source 4. gate 5. drain 6. drain 7. drain 8. drain style 14: pin 1. n-source 2. n-gate 3. p-source 4. p-gate 5. p-drain 6. p-drain 7. n-drain 8. n-drain style 13: pin 1. n.c. 2. source 3. source 4. gate 5. drain 6. drain 7. drain 8. drain style 15: pin 1. anode 1 2. anode 1 3. anode 1 4. anode 1 5. cathode, common 6. cathode, common 7. cathode, common 8. cathode, common style 16: pin 1. emitter, die #1 2. base, die #1 3. emitter, die #2 4. base, die #2 5. collector, die #2 6. collector, die #2 7. collector, die #1 8. collector, die #1 style 17: pin 1. vcc 2. v2out 3. v1out 4. txe 5. rxe 6. vee 7. gnd 8. acc style 18: pin 1. anode 2. anode 3. source 4. gate 5. drain 6. drain 7. cathode 8. cathode l h x 45? c seating plane s b m 0.25 a s c b a1 c a 0.10 1 4 5 8 m b m 0.25 d e h a b e dim min max millimeters a 1.35 1.75 a1 0.10 0.25 b 0.35 0.49 c 0.19 0.25 d 4.80 5.00 e 1.27 bsc e 3.80 4.00 h 5.80 6.20 h 0? 7? l 0.40 1.25 q 0.25 0.50 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions are in millimeter. 3. dimension d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.127 total in excess of the b dimension at maximum material condition. seating plane 0.49 16x b m 0.25 a t 0.35 1.75 1.35 0.25 0.10 6 t 16x 0.1 t 1.27 14x 89 116 8x 6.2 5.8 m 0.25 b 4 10.0 9.8 a 4.0 3.8 b p in 1 index pin's number 5 a a 0.50 x45? 0.25 7? 1.25 0.40 0? 0.25 0.19 section a-a notes: 1. dimensions are in millimeters. 2. dimensioning and tolerancing per asme y14.5m, 1994. 3. datums a and b to be determined at the plane where the bottom of the leads exit the plastic body. 4. this dimension does not include mold flash, protrusion or gate burrs. mold flash, protrusion or gate burrs shall not exceed 0.15mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. 5. this dimension does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. 6. this dimension does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed 0.62mm. d suffix 16-lead soic package case 751b-05 issue k d suffix 8-lead soic package case 751-06 issue t f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC962305 mpc962309 timing solutions 8 motorola package dimensions section n-n j j1 k k1 case 948j-01 issue o date 08/21/95 dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0? 8? 0? 8? ____ notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. see detail e -w- seating plane c d h g 0.10 (0.004) -t- ident. pin 1 1 4 8 5 b a l 2x l/2 -u- s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t -v- 8x ref k detail e f m 0.25 (0.010) n n dt suffix 8-lead tssop package case 948j-01 issue o f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC962305 mpc962309 motorola 9 timing solutions package dimensions dt suffix 16-lead tssop package case 948f-01 issue o section n-n j j1 k k1 case 948f-01 issue o date 12/20 / dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0? 8? 0? 8? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. seating plane c d h g 0.10 (0.004) -t- ident. pin 1 1 8 16 9 b a l 2x l/2 -u- s u 0.15 (0.006) t u 0.15 (0.006) t u m 0.10 (0.004) v t -v- 16x ref k detail e -w- detail e f m 0.25 (0.010) n n s s s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC962305 mpc962309 timing solutions 10 motorola notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC962305 mpc962309 motorola 11 timing solutions notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
information in this document is provided solely to enable system and software implem enters to use motorola products. there are no express or implied copyright licenses granted hereunder to desig n or fabricate any integrated circuits or integrated circuits based on the informa tion in this document. motorola reserves the right to make changes without further noti ce to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or s pecifications can and do vary in different applications and actual performance may var y over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola pro ducts are not designed, intended, or authorized for use as compon ents in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and di stributors harmless against all claims, costs, damages, and expenses , and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim a lleges that motorola was negligent regarding the design or manufa cture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are t he property of their respective owners. ? motorola, inc. 2004 how to reach us: usa/europe/locations not listed: japan: motorola japan ltd.; sps, technical information center motorola literature distribution 3-20-1 minami-azabu. minato-ku, tokyo 106-8573, japan p.o. box 5405, denver, colorado 80217 81-3-3440-3569 1-800-521-6274 or 480-768-2130 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors MPC962305 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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